The present invention generally relates to power-on reset circuits and in particular, to a low standby current power-on reset circuit.
Power-on reset (POR) circuits are useful for indicating to other circuits in a system that power to the system has been turned on, or the system has been reset. In particular, the POR circuit will produce a falling (or rising) edge on an output or power-on reset indication when power (VDD) ramps up to a sufficient level to allow for circuit operation. Upon receipt of such power-on reset indication, the other circuits may then perform various useful functions such as resetting latches and performing start-up operations.
A low standby current POR circuit is further useful in applications where power consumption is to be minimized. Although feedback solutions are commonly employed to reduce the DC current in conventional POR circuit designs, such solutions are difficult to optimize over operational voltage and temperature ranges. This is because, they generally require very critical device sizing on the feedback devices.
Also, a practical retriggering capability for the POR circuit is also useful so that undesirable delay is avoided when retriggering the system. A practical retriggering capability in this case is understood to mean the ability to reproduce the correct power-on reset indication after the power supply (or line) has fallen below a critical level that can cause circuit operation to fail and then has risen above this critical level again.
Accordingly, it is an object of the present invention to provide a low standby current power-on reset circuit.
Another object is to provide a low standby current power-on reset circuit that exhibits practical retriggering capability.
These and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a power-on reset circuit comprising: an output stage circuit providing a power-on reset indication on an output line while a gate-to-source voltage of an output transistor in the output stage circuit is near a threshold voltage so as to turn the output transistor on with minimal current passing through the output stage circuit; and a charging circuit coupled to a power line and the output stage circuit so as to generate and hold the gate-to-source voltage of the output transistor when power to the power line is turned on or reset.
Another aspect is a power-on reset circuit comprising: an output stage circuit providing a power-on reset indication on an output line while a gate-to-source voltage of an output transistor in the output stage circuit is near a threshold voltage so as to turn the output transistor on with minimal current passing through the output stage circuit; and means for generating and holding the gate-to-source voltage of the output transistor when power to a power line is turned on or reset.
Still another aspect is a power-on reset circuit comprising: an output circuit including a capacitor responding to power on a power line being turned on or reset to drive generation of a power-on reset indication; and a discharge circuit coupled to the power line and the capacitor for discharging the capacitor when a voltage on the power line drops below a predetermined level.
Additional objects, features and advantages of the various aspects of the invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.